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VLSI Sys Design
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Course Info
VLSI System Design (17-32-420-01) - Fall Semester 2008
Class discussions: http://groups.google.com/group/iutvlsidesign?lnk=gcimh-http://groups.google.com/group/iutvlsidesign (email to iutvlsidesign@googlegroups.com )
Course web page: http://ece.iut.ac.ir/faculty/kia/Courses/VlsiDesign
Using Magic Instructions: How to run Magic. How to print layouts from Magic.
Class: MW 3:00-4:30pm.
Midterm exam: TBA.
Final exam: 1387/10/15_8, 08:30 - 11:30, open book, open notes.
Catalog Description:
Basic CMOS transistor, static/dynamic circuits, layout and simulation. CMOS arithmetic logic units, high-speed carry chains, fast CMOS multipliers. High-speed parallel shifters. CMOS memory cells, array structures, read/write circuits. Design for testability, including scan design and built-in self test. System-level timing and power optimization.
Text:
None required, [Rab02] highly recommended
| [Rab02] | J. M. Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice Hall, 2nd edition, 2002, ISBN: 0130909963. |
| [WE92] | N. H. E. Weste, K. Eshraghian, "Principles of CMOS VLSI Design: A System Perspective", Addison-Wesley, 2nd Ed., 1992. |
| [Par00] | B. Parhami, "Computer Arithmetic: Algorithms and Hardware Designs", Oxford University Press, 2000. |
Administrative
Please check the "Announcements" link regularly.
Personnel:
Instructor |
Kia Bazargan
|
||||||||
|
. Mohammad Tahghighi
|
Course Outline
-
Basic CMOS circuits
- Basic CMOS transistors
- Static / Dynamic design
- CMOS Design
-
Arithmetic and logic unit (ALU)
- Control path
- Data path layout
- Bit-wise operations
- Adders
- Basic adders: carry propagation, Manchester Carry Chains
- [optional] More complex adders: Carry Look-ahead, Carry Save Adder, Brent-Kung
- [optional] Fast adders: Carry-Select adder, Wallace tree
- Shift/Add multiplication
- [optional] Booth encoding
- [optional] Multiplication by constants
- [optional] Division / Square root
- Multipliers
- Memory cells: Static, dynamic, content-addressable
- Memory arrays: address decoders, sensors and amplifiers
- Shift/rotate operations
- Memory design
- Fault models
- Design techniques: scan design, built-in self-test
- CORDIC algorithms
- Bit-serial computations
- Recent circuit examples
- Test and testability
- [optional] New design techniques
Course Schedule (approx)
| Week # | Lecture topics | Chapter |
| 1 |
Introduction Design methodologies Implementation platforms FPGA architectures |
[Rab96] Ch 11, [WE92] Ch 6 |
| 2-4 |
Basic CMOS design Static logic Dynamic logic |
[We92] Ch |
| 5-7 (2½ weeks) | Adder design | [Rab96] Ch 7, [WE92] Ch 8, [Par00] Ch 5-7 |
| 8 | Multiplier design | [Rab96] Ch 7, [WE92] Ch 8, [Par00] Ch 9-11 |
| 9 (½ weeks) | Control path and data bus design | [WE92] Ch 8 |
| 10-11 | Memory design | [Rab96] Ch 6, 10, [WE92] Ch 8 |
| 12-13 | Testing | [WE92] Ch 7, [Rab96] Ch 11 |
| 14 | Timing | [Rab96] Ch 9 |
| 15 | Power | - |
Prerequisites:
.
Grading Policy:
- Cheating of any kind is extremely serious and may result in a course grade of F and/or expulsion from the University.
-
Homework submissions are due before class starts (or in instructor's mailbox 5 minutes before class).
- You have three days of grace period that you can use however you want (e.g., all three for one homework, half a day for six homework assignments)
- After the grace period is used up, NO grade will be given to late homework.
- Collaboration on homework problems OK, copying not OK.
- Include your name on all homework assignments and exams.
- No extra work will be accepted for improving the final grade
Grading:
- 40% Homework and quizzes - no late homework, no copying!
- 25% Midterm - open note.
- 35% Final exam
Time:
.
Term:
Fall Semester 2008
Grade:
other